11 b 200 MS/s 28-nm CMOS 2b/cycle successive-approximation register analogue-to-digital converter using offset-mismatch calibrated comparators

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive-approximation register (SAR) analogue-to-digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high-resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor-resistor (C-R) hybrid digital-to-analogue converters (DACs). The prototype ADC implemented in a 28-nm CMOS process demonstrates measured differential and integral non-linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1-V supply voltage.