Codelet Pipe: Realization of Dataflow Software Pipelining for Extended Codelet Model.

Dataflow Software Pipelining for Codelet Model is a coarse-grained code-mapping scheme designed to exploit pipelined parallelism across Codelets executing on different cores. The extended operational semantics of the Codelet model exploit pipelined parallelism across loops (coarse-grained) using single owner FIFO buffers across Codelet’s dependencies. The extended Codelet Model with Dataflow Software Pipelining extensions has shown promising performance benefits by leveraging FIFO buffers to communicate between producer and consumer codelets. These performance gains can be further amplified using an efficient implementation of FIFO buffers using hardware-software co-design principles for an architecture that supports explicit access to scratchpad memory closer to compute cores. In this work, we introduce Codelet Pipe which serves as an efficient hardware-software co-designed communication channel between producer-consumer codelets to take advantage of dataflow software pipelining for codelet model. The current implementation of Codelet Pipe exploits Shared Local Memory architectural feature of Intel Iris Pro GPU using OpenCL. Codelet Pipe enables users to construct well-structured Codelet Graphs as well as helps with the challenge of ease of Programmability by relieving user from the responsibility of handling communication between producer-consumer codelet pairs. We demonstrate performance gains using a set of micro-benchmarks for a GPU architecture of strategic importance for exascale supercomputers.