RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature

Q. Berlingard,M. Moulin, J.-P. Michel, T. Fache, I. Charlet, C. Plantier, Z. Chalupa, J. Lugo-Alvarez, J.-P. Raskin,L. Hutin, M. Cassé

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)(2023)

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摘要
We investigate the temperature-dependent RF response of different types of silicon substrates (standard, high-resistivity and trap-rich) through measurements performed on BEOL-embedded inductors from room temperature down to 7K. For the first time, we observe that the performance ranking between substrates, well known at 300K, is altered in cryogenic conditions (T<50K). Based on a parametric analysis of the Q-factor, we attribute this behavior to the heightened importance at low T of counteracting a parasitic surface conduction (PSC) forming at the interface between the substrate and the dielectric.
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关键词
RF substrates,cryogenic measurement,Standard silicon substrate,High-Resistivity silicon substrate,Trap-Rich silicon substrate,CryoCMOS,inductors,High-Q inductor
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