DCT Implementation on a Custom FPGA RISC-V Processor

This paper presents our implementation of an Out-of-Order RISC-V core design. The increasing relevance of open-standard computer architectures and corresponding tools makes the development of custom hardware an increasingly attractive alternative to off-the-shelf components. RISC-V is such an open Instruction Set Architecture (ISA) that has become widely used in recent years, especially in low-cost microcontrollers, but also in high-performance computing in recent years. Here we showcase a custom-developed core capable of executing the Discrete Cosine Transform algorithm which gives the core potential uses in image and video processing. Problems with developing such a core are presented and future possibilities and improvements are discussed.