An FPGA-based edge computing and accelerating platform for fast diabetic retinopathy diagnosis

Diabetic retinopathy (DR) is one of the leading causes of blindness. Early DR screening may significantly reduce the risk of vision impairments. Traditional DR diagnosis relies on a professional ophthalmologist to examine the fundus image of a potential patient. However, in remote and underdeveloped areas, medical resources are relatively limited, hindering professional and timely DR diagnosis. In such context, there is an urgent need to develop convenient and fast DR screening methods to provide effective intervention plans. In this work, we implemented and validated a real-time DR diagnosis system on field-programmable gate array (FPGA) board. We first trained a DR grading CNN of interest on GPUs, and then deployed it on FPGA after quantization. Two CNN architectures, ResNet50 and MobileNetV2, are investigated. With 16-bit quantization, ResNet50 and MobileNetV2 respectively achieve 0.828 and 0.753 Kappa scores on the publicly-accessible EyePACS test set. Improvements in average processing time have also been observed: 16.92ms over CPU and 0.21ms over GPU.