A Partial-Givens-Rotation-Based Symbol Detector for GSM MIMO Systems: Algorithm and VLSI Implementation

Recently, generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems have attracted intensive research interest due to their advantages in balancing spectral efficiency and interchannel interference. Aiming at satisfactory detection performance based on a feasible hardware architecture, in this paper, a partial Givens rotation (PGR)-based symbol detector with a very-large-scale integration (VLSI) hardware architecture is proposed for GSM MIMO systems. The proposed detector contains three main types of modules: PGR blocks, symbol estimation (SE), and minimization. In particular, compared to conventional Givens rotations (GRs), the proposed PGR mechanism can further reduce computational complexity by at least 36 $ \%$ . In addition, to ensure numerical stability, only adders, shifters, and comparators are used to implement the SE architecture, avoiding the use of dividers. Furthermore, instead of the 2-norm distance measure, the 1-norm distance measure is used in the proposed detector to reduce the number of multipliers, thereby accelerating the detection speed. Finally, computer simulations showthat the proposed algorithm performs achieves near-optimal performance while incurring a lower computational complexity. Additionally, hardware implementation results achieved in TSMC 90-nm CMOS technology at an operating frequency of 704.2 MHz, with a configuration of four transmit antennas, two active transmit antennas, four receive antennas, and 16-ary quadrature amplitude modulation (16-QAM), show that the proposed hardware architecture needs 395.2 k gates and provides a detection throughput of 2347 Mbps and a hardware efficiency of 5.94 Mbps/kGEs for fast fading channels. In comparison to existing works, the proposed detector provides attractive detection performance as well as a feasible hardware architecture.