Iterative pruning algorithm for efficient look-up table implementation of binary neural networks

The implementation of deep neural networks requires a significant amount of memory and computing power. As a result, they are often implemented in data centers or highend computing devices such as GPUs. However, if the internal structure of an FPGA, particularly the LUTs, is considered, the FPGA implementation of these networks could prove to be more efficient. This paper presents an iterative pruning algorithm for removing unnecessary inputs from a layer's neurons so that they can be synthesized to a small number of LUTs in an FPGA. When the number of LUTs, throughput, and power consumption are considered, our design is 7.95x smaller, 1.66x faster, and 5.66x more power efficient than the baseline, with a 0.47% accuracy drop.