Design and Implementation of an FFT-Based Neural Network Accelerator Using Rapid Single-Flux-Quantum Technology

Deep neural networks (DNNs) are continually expanding in size and complexity, making it essential to enhance their energy efficiency and performance without sacrificing accuracy. The model size significantly influences the performance, scalability, and energy efficiency of DNNs, which has led to increased interest in model compression and hardware acceleration research. This paper presents a novel convolution processor architecture specifically designed for a block-circulant matrices-based neural network processing approach. The proposed design employs ultra-fast (tens of gigahertz) superconductor-based devices and leverages fast Fourier transform (FFT)-based rapid multiplication, achieving a simultaneous reduction in both computational complexity and storage complexity from O(n(2)) to O(n log n). To validate the concept, we implement a 7-bit, 8-point convolution processing element (CPE) based on the proposed architecture, demonstrating high-speed operation up to 43.1 GHz. The implemented circuit consists of 21,575 Josephson junctions and is fabricated using a 10kA/cm(2) 9-layer niobium superconductor process.