A 90-nm CMOS 800 MHz 2 × VDD output buffer with leakage detection and output current self-adjustment

This work presents a 800 MHz 2 × VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43