26TSPC: A Low Hold Time, Low Power Flip-Flop With Clock Path Optimization.

Recent low-power flip-flops (FFs) synthesize a signal (CKN) that is activated only when the input data (D) updates the output state (Q). It saves power consumption by avoiding unnecessary transitions in internal nodes. However, the circuit for CKN that removes all redundant transitions becomes complex. As a result, its delay worsens timing parameters (setup time, hold time, CK_Q delay) and the robustness of FFs too. By optimizing the delay of the clock insertion paths, the presented flip-flop (26TSPC) maximizes efficiency without speed degradation, while maintaining low hold time. Its design is based on 18TSPC, one of the fast and energy-efficient FFs, and its contention and redundant transition issues are also resolved. Post-layout simulation results based on 65 nm CMOS process show that 26TSPC consumes 83.9%/71.4% less power than that of conventional transmission-gate flop-flop (TGFF) with 10%/20% activity ratio at 1V and 75.4%/65.3% less power than that of TGFF with 10%/20% activity at 0.4V respectively. In addition, the hold time of 26TSPC is negative in all corners, featuring better timing reliability than other low-power FFs.