On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI.

ETS(2023)

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摘要
The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead.
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关键词
advanced CMOS technology,area efficiency,back-end-of-the-line interconnects,BEoL interconnects,catastrophic failures,chip silicon lifecycle management infrastructure,current density,decisive impacts,EM profile,EM sensor,energy efficiency,failure prediction,feature sizes,general sensor,in-field monitoring,nanoscale VLSI,on-chip electromigration sensor,preventive maintenance scheduling,realistic SRAM design,remaining lifetime,remaining useful lifetime,running workload,Si/int,size 5.0 nm,transistor feature size,VLSI system
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