Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks.

When paths between computational elements of a digital design do not have the same propagation delay, then signals at the inputs of one of these computational elements could arrive at different moments. Signals arriving early than necessary can create switching activities in the computational element if no action is taken. This leads to consuming power for useless computation. One approach to overcome this situation is to balance the length of all paths using strategies like gate resizing and/or voltage scaling. However, when the computational elements are IP Blocks (blocks from a third party), then the designer is not allowed to optimize inside the computational elements to make paths balanced; instead, buffers can be inserted in some paths while making all the paths of equal length. Inserting buffers will not change the design’s functionality since signals at the input and output of a buffer are the same. We propose an Integer Linear Programming to this problem, which allows inserting a minimal number of buffers, and more than one buffer can be inserted in any path compared to existing approaches. Also, in this paper, computational elements can have different execution delays to produce their output bits, which is not the case in published approaches. Our proposed approach solves the problem for both combinational and clocked sequential digital designs.