Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors.

FPGAs are an increasingly popular medium for many high-performance data center workloads and the rapidly-expanding artificial intelligence domain. These applications often make extensive use of floating-point (FP) numbers defined by the IEEE 754 standard [1]. Although researchers have extensively studied FPGA-based hardware FP implementations, existing work has largely focused on standalone and throughput-optimized data-path designs. Such designs optimize performance by increasing throughput with long pipelines and high frequencies. This approach is not suitable for soft processors, which are more sensitive to latency in order to reduce stalls due to data hazards. Additionally, the frequency ceiling imposed by other internal components of the soft processor necessarily limits the maximum operating frequency of the Floating-Point Unit (FPU).