A 1GS/s Highly Linear Voltage-to-Time Converter with Rail-to-Rail Input Range for Time Domain ADCs
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)（2022）
摘要
This paper presents a highly linear voltage-to-time converter (VTC) with a bottom-plate sampling and voltage-boost scheme to obtain a rail-to-rail input range. A cascode current mirror and a dynamic threshold crossing detector (TCD) are also added to improve the linearity during the discharging process. Simulated in TSMC 28nm CMOS process, the proposed VTC achieves a 63.6-dB SFDR and an 8.4-bit ENOB for a Nyquist input at 1-GHz sampling frequency while consuming 1.5 mW. The input range is +/-900mV and the output range is +/-662ps.
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关键词
bottom-plate sampling,cascode current mirror,discharging process,dynamic threshold crossing detector,linear voltage-to-time converter,Nyquist input,power 1.5 mW,rail-to-rail input range,sampling frequency,size 28.0 nm,time -662.0 ps to 662.0 ps,time domain ADC,TSMC CMOS process,voltage -900.0 mV to 900 mV,voltage-boost scheme
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