A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG

Stochastic computing has shown great promise for a variety of applications, including image processing circuits, due to its design simplicity, and low power consumption. This work proposes a hardware efficient and low-latency implementation of the greatest common divisor (GCD) circuit. It uses a low latency parallel random number generator (LL-PRNG) architecture with an intelligently chosen seed value that eliminates the use of correlators and decorrelators in the circuit, reducing the hardware overhead to a great extent. The proposed approach is compared with the conventional LFSR-based design showing reasonable accuracy while the latency in computation greatly reduced. The circuit is evaluated for blind image deconvolution employing GCD and has shown encouraging results.