ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors

Application Specific Instruction Set Processor (ASIPs) have been proposed in the past to increase the performance while reducing the energy of general-purpose processors. These ASIPs are normally generated at the RT-Level (Verilog or VHDL). In this work we leverage the advantages of High-Level Synthesis (HLS) by designing the complete ASIP in ANSI-C. HLS is a single process synthesis method, thus, the key is to merge the CPU and hardware accelerator descriptions. This allows us proposed flow to synthesize the entire system together, which has numerous advantages like being able to reduce the total area, while further minimizing the power as the HLS process can now fully co-optimize the ASIP by e.g., maximizing resource sharing. Moreover, HLS allows to generate a variety of different implementations by simply setting different synthesis options. We leverage this unique feature in this work to automatically generate ASIPs with different area vs. performance and power trade-offs. Experimental results show that our proposed flow is very effective leading to smaller area overheads than traditional methods, while substantially reducing the energy and increasing the performance as compared to the original general-purpose RISC-V processor and the state of the art.