Temperature Sensitive Analysis of Junctionless Nanowire Ferroelectric Field Effect Transistor (JNFe- FET) for Enhanced Analog Performance

In this manuscript, we propose a study that evaluates the effect of temperature on junctionless nanowire ferroelectric field effect transistor (JNFe-FET). In the present study, it is verified that JNFe-FET exhibits better performance over conventional Junctionless nanowire field effect transistor (JN-FET) in terms of drain current, transconductance and output conductance at various temperatures (100K, 200K,300K, 400K, and 500K). In JNFe-FET, due to the negative capacitance phenomenon, internal voltage amplification takes place which leads to a reduction in subthreshold swing (below 60 mV/decade, Boltzmann Tyranny). The effect of negative capacitance diminishes with an increase in temperature. Electric potential and electric field have also been studied for the proposed model. The simulations have been performed using the ATLAS 3-D device simulator.