Potential and Pitfalls of Multi-valued Logic Circuits for Hardware Security

2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS)(2023)

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摘要
The proliferation of information dissemination has generated a need for greater computing resources. While binary logic circuits have the ability to process 2n information states, Multi-Valued Logic (MVL) circuits have the potential to process information states exponentially larger than those achievable by binary logic. MVL circuits also possess the capability to reduce the complexity, power-delay-product, per unit area, and transistor counts of binary circuits, rendering MVL circuits a compelling substitute for conventional binary logic circuits. However, the adoption of a nascent circuit system presents opportunities for system vulnerabilities to be exploited by malicious actors. In this paper, we conduct a comprehensive survey of the current state of research on MVL gates, modules, and the requisite devices for building MVL circuits. Furthermore, we explore the prospective implications of MVL circuits in the context of hardware security, including but not limited to side-channel attacks, security primitives, and logic locking. Additionally, we evaluate the attendant challenges that arise in implementing MVL circuits in existing systems.
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关键词
Multi-valued logic(MVL),ternary logic,2D materials,hardware security,hardware attacks,side-channel attacks
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