FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS(2023)

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摘要
Design flows are the explicit combinations of design transformations, primarily involved in synthesis, placement, and routing processes, to accomplish the design of integrated circuits (ICs) and system-on-chip (SoC). Mostly, the flows are developed based on the knowledge of the experts. However, due to the large search space of design flows and the increasing design complexity, developing intellectual property (IP)-specific synthesis flows providing high quality of result (QoR) is extremely challenging. In recent years, machine learning (ML) has been increasingly used in electronic design automation (EDA), with the goal of reducing manual labor and speeding up the design closure process in current toolflows. Existing techniques, on the other hand, either necessitate a huge amount of labeled data and time-consuming training, or are constrained in terms of practical EDA toolflow integration due to computational overhead. This article presents a generic end-to-end sequential decision making framework FlowTune for synthesis tooflow optimization, with a novel high-performance domain-specific, multistage multiarmed bandit (MAB) approach. This framework addresses a wide range of optimization problems on Boolean optimization problems, such as And-Inv-Graphs (AIGs), conjunction normal form (CNF) minimization (# clauses) for Boolean satisfiability; logic synthesis and technology mapping, and, more importantly, end-to-end post place-and-route (PnR) optimizations. Moreover, we demonstrate the high extensibility and generalizability of the proposed domain-specific MAB approach with end-to-end FPGA design flow, evaluated at post-routing stage, with two different FPGA backend tools (OpenFPGA and VPR) and two different logic synthesis representations [AIGs and Majority-Inv-Graph (MIG)]. FlowTune is fully integrated with ABC (Mishchenko et al., 2010), Yosys (Wolf, 2016), VTR (Luu et al., 2014), LSOracle (Neto et al., 2019), OpenFPGA (Tang et al., 2019), and industrial tools, and is released publicly. The experimental results conducted on various design stages in the flow all demonstrate that our framework outperforms both handcrafted flows (Mishchenko et al., 2010) and ML explored flows (Yu et al., 2018), (Hosny et al., 2019) in QoRs, and is orders of magnitude faster compared to ML-based approaches.
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关键词
Circuit synthesis,design automation,machine learning
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