Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In₂O₃ FETs Toward Monolithic 3-D Integration

In this work, the transient thermal and electrical characteristics of top-gated (TG), ultrathin, atomic-layer-deposited (ALD), back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors on various thermally conductive substrates are co-optimized by visualization of the self-heating effect (SHE) utilizing an ultrafast high-resolution (HR) thermo-reflectance (TR) imaging system and overcome the thermal challenges through sub-strate thermal management and short-pulse measurement. At the steady-state, the temperature increase (delta T) of the devices on highly resistive silicon (HR Si) and diamond substrates are roughly 6 and 13 times lower than that on a SiO2/Si substrate, due to the much higher thermal conductivities (kappa) of HR Si and diamond. Consequently, the ultrahigh drain current (I-D) of 3.7 mA/mu m at drain voltage (V-DS) of 1.4 V with direct current (dc) measurement is achieved with TG ALD In2O3 FETs on a diamond substrate. Furthermore, transient thermal study shows that it takes roughly 350 and 300 ns for the devices to heat-up and cool-down to the steady-states, being independent of the substrate. The extracted thermal time constants of heat-up (tau(h)) and cool-down (tau(c)) processes are 137 and 109 ns, respectively. By employing electrical short-pulse measurement with a pulsewidth (t(pulse)) shorter than tau(h), the SHE can be significantly reduced. Accordingly, a higher ID of 4.3 mA/mu m is realized with a 1.9-nm-thick In2O3 FET on HR Si substrate after co-optimization. Besides, to integrate BEOL-compatible ALD In2O3 transistors on the front-end-of-line (FEOL) devices with the maintenance of the satis-factory heat dissipation capability, a FEOL-interlayer-BEOL structure is proposed where the interlayer not only electrically isolates the FEOL and BEOL devices but also serves as a thermally conductive layer to alleviate the SHE.