A Low-Power Common-Mode Detector with PVT-Compensation Technique for Dynamic Amplifier in Delta-Sigma Modulator

A low-power common-mode detector (LPCMD) with process, supply voltage and temperature (PVT)-compensation technique for the dynamic amplifier in delta-sigma modulator (DSM) is proposed. By adopting the varying supply voltages to compensate the variation of the transistors’ threshold voltage, the proposed LPCMD improves the robustness of the dynamic amplifier (DA). Additionally, the auxiliary circuit providing the varying supply voltages is realized by the low-power regulator, which has the advantage of low power and low complexity. To demonstrate the feasibility of the proposed LPCMD with the PVT-compensation technique, a second-order 2-bit quantization-based DSM is designed in 180 nm CMOS technology and the postlayout simulation is performed. The DSM achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic range (SFDR) of 93 dB and 95 dB at the sampling frequency of 204.8 kHz, respectively, with the power consumption of 11 µW, leading to a 171.6 dB SNDR-based Schreier figure-of-merit (FoM SNDR ). Furthermore, the SNDR degradation of the DSM under all process corner and temperature from − 40 to 125 ℃ is less than 3 dB. The postlayout simulation result of the DSM verifies the feasibility and effectiveness of the proposed LPCMD and PVT-compensation technique.