Quantitative Analysis of Sparsely Synchronized Fail-Safe Processors.

We present the design and fail-safety analysis of a sparsely synchronized N-modular redundant architecture for fail-safe computing that can be built on unreliable commercial off-the-shelf (COTS) components. Though the main intended audience is railway operators, the architecture is expected to be useful for general fail-safe computations. Traditional bus-synchronized fail-safe processors have had difficulty catching up with the performance and cost improvements of COTS processors because frequent involvement of the voter needed specialized design that slowed down computations. The proposed architecture alleviates this problem by comparing data much less frequently, only when the data leaves the fail-safe processor altogether. This allows the voter to be vastly simplified, becoming easy to harden against errors. We show empirically the use of COTS hardware barely affects the reliability of the overall architecture, making it as reliable as the simple voting circuitry, with acceptable runtime overhead.