Stepwise Debugging for Hardware Accelerators.
ASPLOS (2)(2023)
摘要
High-level programming models for hardware design let domain experts quickly produce specialized accelerators.
However, tools for debugging these accelerators remain tied to low-level hardware description languages (HDLs).
High-level descriptions contain control-flow information that is lost in HDL code.
We describe Cider, a stepwise debugger that exploits this information to provide software-like debugging abstractions for languages that compile to hardware.
Cider uses Calyx, an intermediate language
for accelerator generators that preserves control information.
Cider provides breakpoints, watchpoints, state inspection, and source-level position mapping.
Using case studies that examine one new and two preexisting accelerator generators,
we demonstrate how Cider helps find and localize
previously unreported bugs.
By directly simulating a control-rich representation, Cider avoids
wasting effort on inactive parts of the design and, despite being largely unoptimized, performs competitively with open-source HDL simulators.
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关键词
Intermediate Language, Accelerator Design, Debugging, Accelerator Simulation
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