FPGA Implementation of Batch-Mode Depth-Pipelined Two Means Decision Tree

Decision tree for classification tasks are learned from the input dataset and consist of split nodes and leaf nodes. This letter presents the hardware implementation of learning of two means decision tree (TMDT). To accommodate large-size datasets and hence, to increase accuracy, the training data is divided into small batches and one batch at a time is loaded into chip memory. The hardware is divided into two pipelines to optimize timing and resource consumption. The critical path of the architecture enables the field-programmable gate array (FPGA) to operate with maximum frequency of 62 MHz. Simulation results show that the proposed FPGA runs at least 27x and 26x faster than the C implementation and existing hardware, respectively.