Simulation of Transport Moiré Pattern in Van Der Waals Heterostructures

Vertically stacking two-dimensional (2D) materials with different lattice constants will generate a Moiré pattern with a nanometer-scale periodicity. Here, we theoretically demonstrate the transport Moiré patterns on the surfaces of stacked 2D materials. In the MOSFET model, the electrons accumulate at high Moiré potential regions, while they dissipate at the others, along the gate voltage ( ${V}_{g}{)}$ until high current levels. As an application of the inhomogeneous transport, we show that the Moiré pattern can be used to restrain the effect of edge defects in one-dimensional ribbons by modulating the potentials of the edge and middle regions. Simulation results show that the ${V}_{g}$ deviations can be substantially reduced when different kinds of edge defects are randomly added, such as vacancies and foreign dopants, suggesting the suitability of Moiré pattern in defect engineering.