DPLL-Based VRO of Time-to-Digital Converter

A time-to-digital converter (TDC) uses a digital phase-locked loop (DPLL)-based vernier ring oscillator (VRO) (PLL-based VRO). For a VRO, the timing resolutions of the coarse-tuning process (CTP) and the fine-tuning process (FTP) have a proportional relationship under the process, voltage, and temperature (PVT) variations. The delay time (sum of rise time and fall time) of the inverter can define the timing resolutions of CTP and FTP. Therefore, the timing resolution ratio between CTP and FTP is a constant under the PVT variations. For a high timing resolution, the VRO adopts a divider (/ $M$ ) to extend the timing resolution. The DPLL can provide a specific timing resolution for the VRO, when the digitally controlled oscillator and the VRO adopt the same oscillator’s schemes. This 14-bit TDC was fabricated in a 90-nm CMOS process. The measured timing resolution is 18 ps at $M\,\,=$ 10. The TDC input ranged from 1 to 206 ns and the power consumption was 2.5 mW.