An Instruction-configurable Post-quantum Cryptographic Processor towards NTRU

Post-quantum cryptography (PQC) is proposed to resist the attack of quantum computer. Among various PQC schemes, lattice-based cryptography depended on learning with errors (LWE) problem has attracted much attention. As one of the lattice-based PQC schemes, number theory research unit (NTRU) algorithm is flexible, simple and fast. In this paper, we propose a high-performance cryptographic processor towards NTRU. In the processor, we optimize instruction set architecture, which also saves memories. Three-level Karatsuba method is utilized to accelerate polynomial multiplication, and the computing time is reduced by 10x. Fixed and custom instructions are used to control the whole data path, with flexibility and high efficiency. Compared to other FPGA implementations, the results show this design performs the highest operating frequency of 200MHz, only consumes 28k look-up tables (LUTs). Besides, it has the shortest time of encryption, decryption and the best area-time product (ATP), which is 1.4x better than state-of-the-art work.