An ultra-area-efficient ALU design in QCA technology using synchronized clock zone scheme

A quantum-dot cellular automaton (QCA) is currently regarded as a radical nanotechnology that is rapidly growing and offering new methods for achieving high-speed computing at the nano-scale. It is an advanced transistor-less nanotechnology, considered for ultra-low-power dissipation, high functioning speed in THz, high device density, and less circuit complexity as a replacement for CMOS technology. This work demonstrates a new circuit design and implementation of the single-bit arithmetic logic unit (ALU) in QCA technology. This can be reduced in terms of the number of quantum cell count, reduced latency, minimization of the design area, optimization of the power consumption and calculation of the effects of temperature on output cell at temperature range 1–7 K by using novel QCADesigner-E (Energy) Version 2.2 tool. The presented ALU design is constructed by 18 × 18 nm QCA cell size, using coherence vector simulation engine setup parameters to provide a regular synchronized clock zone. The proposed design has achieved an improvement of 46.15% of the overall design area, 36.36% of the QCA cell area, and 25.00% of the delay by using the multilayer crossover technique. The proposed design of the QCA–ALU layout and functional verification of the design is performed by using the QCADesigner-E.