Evaluating Cryptographic Extensions On A RISC-V Simulation Environment

Due to the security requirement in the widely-deployed embedded applications, lightweight cryptographic ci-phers have been offered and used in resource-constrained devices in the last decades. In addition to the intrinsic low-cost properties of these ciphers, implementation-and architecture-specific techniques can make the implementation of these ciphers even more efficient. In this paper, we propose a simulation environment for the open-source RISC-V Instruction Set Architecture (ISA) implementing the base RISC-V ISA as well as the “bit manipulation” instruction set extension (ISE), which facilitates the imple-mentation of (lightweight) symmetric cryptography algorithms on resource-constrained devices efficiently. For demonstration pur-poses, we implement the lightweight block ciphers LEA, SIMON, and SPECK on our simulator and evaluate the performance of these ciphers on RISC-V architecture implemented with and without bit manipulation instructions. We define the performance of the lightweight ciphers as the total number of clock cycles required to encrypt one block of plaintext successfully. The performance of lightweight ciphers gives us an insight on how the performance of a cipher can be improved by using specific bit manipulation instructions. Our results show an average 38 % improvement in the total number of clock cycles required to run lightweight ciphers while using bit manipulation instructions.