A Self-Clocked TDC-Based Unified Clock and Voltage Regulator with Replica Frequency-Locked Loop and Hysteresis Switching in 65nm CMOS

Time-to-digital converter (TDC)-based digital low-dropout regulators (DLDOs) [1–5] were developed for process scalability and better trade-off among power consumption, response time and regulation accuracy compared to conventional voltage-based DLDOs. A pair of differential voltage-controlled ring oscillators (VCOs) is commonly used for voltage-to-frequency (V2F) conversion [2–4], but it does not mimic the critical path of a microprocessor and does not guarantee enough time slack due to PVT variations. Alternatively, a tunable replica oscillator (TRO) mimics half of the critical path delay, clocks the microprocessor, and allows error-free operation even during voltage undershoot caused by load transients [6].