Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.

Continuous CMOS scaling enabled by complex transistor topology raises self-heating concerns. Here, we perform a comparative thermal benchmarking of architectures for current and projected device technologies: finFET (iN8–iN5), nanosheet (iN5/iN3), forksheet (iN3) and monolithic CFET (iN2) using an in-house Monte Carlo framework with first-principles heat carrier properties. Experimental validations highlight the impact of non-diffusive thermal transport inside logic cells. Thermal resistance oscillates node by node but grows near linearly with power density. Channel fragmentation (finFET to nanosheet) raises temperatures, while buried power rails help reduce self-heating. Excess channel heating (relative to the cell boundary) of 0.8–1.6 and 10–19 degrees is observed for baseline (0.7VDD at 2GHz clock) and turbo (1.4VDD at 6GHz clock) operation scenarios respectively.