FPGA Implementation of a Linearization System for Wideband Envelope Tracking Power Amplifiers

This article focuses on the implementation of a linearization system for envelope tracking (ET) power amplifiers (PAs) in field-programmable gate array (FPGA). The ET PA linearization system includes a slew-rate reduction envelope generator, a RF leakage cancellation system in the supply envelope path and a baseband I-Q digital predistorter (DPD). This work targets the implementation of an ET PA linearization system on a radio frequency system-on-chip (RFSoC) device running under a demanding baseband sampling frequency of 614.4 MHz, which allows handling communication signals with up to 200 MHz bandwidth, considering a DPD bandwidth expansion by 3x. The detail of the FPGA implementation is presented to illustrate the trade-off between hardware resources and linearization performance, i.e., adjacent channel power ratio (ACPR) and error vector magnitude (EVM), under different bit configurations for the arithmetic. The power consumption is also evaluated since it is another relevant performance indicator to be considered in the FPGA implementation of the linearization system.