Energy-Efficient VLSI Squarer Unit with Optimized Radix-2 m Multiplication Logic

Multipliers are demanded in a variety of applications. They consume higher power than other blocks. On the other hand, squarer units are less complex than a general-purpose multiplier, with wide use in cryptography, image processing, and video coding. This paper presents a new radix-2 m squarer unit. It uses the essential sum trees to avoid redundant operations. Omitting some duplicate multiplications simplifies the final VLSI architecture. This work uses the radix-2 m squarer units with m equal to 2 (radix-4), 3 (radix-8) and 4 (radix-16). We evaluate the proposed squarer units using high-efficiency video coding (HEVC) and cryptography algorithms for a range of bits. For performance results, the architectures use random input vectors. The results show that radix-4 and radix-8 units are more area and power efficient than radix-16 units. Moreover, the high energy savings of our proposed radix-4 and radix-8 units are preserved in the case studies addressed, compared to squarer units from the literature. Particularly, we show that radix-4 and radix-8 provide more energy savings in computing sum of squared differences (SSD). Furthermore, radix-4 and radix-8 squarer units are also efficient in the Montgomery-ladder architecture, reducing energy by 58.76% (radix-8) and 63.39% (radix-4) compared to the multiplier automatically selected by the logic synthesis tool.