Area and Power analysis of a Scalable Primitive Polynomial computation circuit over the field GF(2)

Primitive polynomials are important in hardware realizations for error control codes, cryptography, and other signal processing and communication-based designs. These primitive polynomials over a finite field in association with the core concepts of a particular area of study can be easily implemented on hardware. Researchers have used existing databases of primitive polynomials of various degrees in most cases, generated using a software-based logic. However, not much study has been carried out to implement the logic for computation of primitive polynomials on hardware. This paper describes an implementation of a scalable primitive polynomial circuit. The circuit can compute the primitive polynomial of any degree for a finite field and uses shift registers for the said purpose. This scalable circuit is synthesized on ASIC with a 45 nm CMOS process using Synopsys Design Compiler to assess standard cell area and power. The standard cell area and power consumed by the scalable circuit for various degrees of the primitive polynomial are also analyzed in this paper.