A 56GHz 23mW Fractional-N PLL with 110fs Jitter.

PAM-4 wireline transmitters operating at 224Gb/s can employ a 56GHz PLL for multiplexing. Such an environment poses several constraints on the design. First, the PLL rms jitter must be no more than a few percent of the symbol period, 8.93ps, dictating values around $100\text{fs}_{\text{rms}}$ . Second, the PLL should preferably provide fractional-N operation so as to accommodate different crystal frequencies. Third, in a multi-lane system, it is desirable to avoid distributing a 56GHz clock over long interconnects, hence the need for a lower-power, compact PLL that can be used within each lane. Prior fractional-N designs in this frequency range have achieved rms jitters ranging from 200 to 500fs while consuming beween 31 and 46mW and occupying areas from 0.38 to 0.55mm2 [1]–[4]. This paper introduces a PLL with a jitter of 110fs that draws 23mW and occupies an area of 0.1 mm ² in 28nm CMOS technology.