An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs

In this article, an active slew rate (SR) control IC for superjunction MOSFET (SJMOS) is proposed. Active gate control is an attractive technique to reduce switching (SW) losses by maintaining a constant drain voltage SR ( $dV_{d}/dt$ ) of power devices. However, the conventional method for IGBT, GaN, and SiC devices cannot be applied to the active gate control of SJMOS because $dV_{d}/dt$ is determined by the reverse recovery current ( $I_{\mathrm {RR}}$ ), which is unique to SJMOS. In this article, a discrete-time feedback technique that can control $I_{\mathrm {RR}}$ generated before the drain voltage transition by reflecting the feedback result in the next SW is proposed. The $dV_{d}/dt$ of SJMOS is kept constant by controlling $I_{\mathrm {RR}}$ with two resistors connected to the gate. In addition, the proposed technique can reduce the SW losses more than the control with one resistance value under the same $dV_{d}/dt$ condition because the proposed technique can improve the rise time of the drain current without changing $dV_{d}/dt$ . By using the proposed technique, $dV_{d}/dt$ can be kept constant regardless of the load current, temperature, and threshold voltage of SJMOS. The proposed gate driver is implemented in 0.6- $\mu \text{m}$ CMOS, and the measured results show that $dV_{d}/dt$ can be controlled to 3, 4.5, and 4.9 V/ns values, and the SW losses can be reduced by 25%. The turn-on delay reduction of 74% is also achieved by the proposed gate driver.