Resist line edge roughness mitigation for high-NA EUVL

The next-generation extreme ultraviolet (EUV) lithography tool, i.e., the high-numerical aperture (NA) ASML EXE system is now under preparation. As a consequence of the 0.55 NA, EXE scanners decrease the depth-of-focus (DoF) drastically, which requires much thinner photoresist thickness. However, a thinner photoresist process causes line edge roughness (LER) increase. Therefore, roughness mitigation is one of the key elements of high-NA EUV process development. We have studied how to heal LER of thin photoresist processes by illumination and mask. Rigorous simulations were conducted by Sentaurus EUV lithography (TM) (S-litho EUV) software provided by Synopsys on a calibrated stochastic Inpria metal oxide resist (MOR) model to adopt the correct photoresist parameter set. Unbiased LER values were experimentally measured on half pitch (hp) 14 nm and 24 nm line and space (LS) as a function of normalized image log slope (NILS) and photoresist film thickness. 24nm hp on 0.33 NA corresponds to 14nm hp on 0.55 NA from the viewpoint of k1 factor (similar to 0.57). NILS of these LS patterns was varied by changing illumination (dipole and annular). By comparing the experimental LER values on silicon with the simulated results, we predicted the LER performance of high-NA EUVL on 14nm hp LS pattern. In this research, we will discuss the better material condition for reduced LER of fine LS pattern at high-NA EUVL.