AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design

For FPGA circuit design, exploring the FPGA design space for the optimal performance becomes important and also challenging. The popular tool COFFE was built on an academic architecture and cannot be applied to modern commercial FPGA chips with the general routing matrix (GRM) architecture. In this paper, we report the design, implementation, and evaluation of our Automated Transistor-level Efficient and Accurate tool, AutoTEA, which extracts the key sub-circuits, uses the initial transistor sizes to construct hspice netlists, and finds the optimal circuit transistor sizes. AutoTEA features accurate area and delay models, and a fast solution space exploration method. We evaluate the accuracy of the area model by comparing with the layout area of a GRM FPGA chip in 28 nm technology. The average area estimation errors are −0.39%, 35.52%, and 9.18% for AutoTEA, COFFE, and a transistor-level automated tool for GRM architecture, respectively. Our load model gives us delay with an average error of −0.90% of the post-simulation delay, while COFFE's average error is 25.75%. Experimental results show that AutoTEA has a speedup of 20X and 2.7X over COFFE and an optimization tool for GRM architecture. Using a cost function that considers both area and delay, we show that AutoTEA is able to improve the area delay product of a previously manually optimized GRM FPGA design by 11%.