Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques

The IEEE 1687 Std. (IJTAG) introduces an efficient access methodology based on reconfigurable scan networks to address the ever-increasing complexity of the latest system-on-chips. By invoking this new methodology, the overall test time can considerably be reduced by shortening the scan chains' length without sacrificing the test quality. IJTAG allows for designing highly complex test networks compromising the latest test structure that enables to achieve the high test quality, as required by today's customers' applications. Besides the time overhead induced by the required network (re-)configuration, the access sequence of the instruments itself greatly affects the overall test time. Furthermore, the power characteristics of the complex test facilities have to be taken into account to avoid effects like IR drop during the later test application that is even more critical in highly multi-power domain networks. Consequently, the IJTAG methodology strictly requires an effective test scheduler that considers the individual instruments' constraints and is compatible with recent multi-power domain chip designs. This work proposes two novel power-aware test scheduling approaches based on pseudo-Boolean optimization and integer linear programming techniques that are both seamlessly integrated into a fully-automated test scheduling framework for IJTAG test networks even with multiple power domains. The first proposed optimization scheme allows for determining a local optimal test schedule, applicable to networks with more than one thousand instruments since the required run-time is manageable. Furthermore, the second optimization scheme determines a global optimal test scheduler, which is most suitable for mid-sized networks in which it is clearly outperforming any other existing technique.