Hardware and Software Implementation of H.256 CABAC Encoder/Decoder

Video compression is an essential operation in Ultra High Definition (UHD) real time applications. Several techniques for video compression exist nowadays, but the H.265 standard is latest one. High Efficiency Video Coding (HEVC) or H.265 codec is becoming the most important consumer application platforms in the current days. Compared with its predecessor AVC (Advanced Video Codec) standard, it can support the UHD picture at 120 fps. HEVC adopt many advanced techniques such as SAO filter, intra and inter prediction and Context-based Adaptive Binary Arithmetic Coding (CABAC). CABAC is considered as sole entropy coding used in H.265 codec. In this work, we propose hardware and software implementation of HEVC CABAC encoder. First the algorithm is implemented on MATLAB software for controlling the encoding process. Second, in hardware implementation the storage and resources cost can be reduced by running multiple arithmetic encoding engines at the low level (coding block) and enabling the pipeline within the arithmetic coding engine. FPGA Synthesis results demonstrate that our proposed architecture can process 2 regular and 5 bypassed bins per cycle to provide the tradeoff between the throughput and the resources cost.