Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O

Test time continues to increase due to the growing design size and complexity of modern large-scale System-on-Chip (SoCs). An increasing adoption of chiplet-based design method further exacerbates this problem as it reduces the number of pins available for test pattern application. Additionally, the SoCs deployed in safety-critical applications require in-system testing with very short test times. In this paper, we introduce a novel solution that addresses these challenges by using the existing high-speed functional interfaces of an SoC, such as PCIe or USB, to perform both scan test and in-system test with easy accessibility. This solution uses the native protocol of these scalable high-speed interfaces to deliver packetized test data to the device-under-test (DUT) at significantly faster speeds than can be achieved using General Purpose Input/Outputs (GPIOs), reducing test time. This paper provides the details of the solution and its practical implementation along with silicon data on an Amazon Machine Learning (ML) SoC.