Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

We report on scaled finFETs with a novel routing scheme enabling connection via buried power rails (BPR) from both wafer sides, with tight variability/matching control. On the frontside (FS), contacting to p/n S/D-epi and BPR is done, after M0A and VBPR vias patterning, in a single metallization step with an optimized preclean reducing R ext while preserving a good BPR-VBPR contact interface. After wafer flipping, bonding and extreme thinning, highly scaled, ~323nm deep nano-through-Si-vias (nTSV) land on BPR, with tight overlay control and unchanged BPR resistance (26-29% lower with improved W-fill). By moving the power delivery network to the backside (BSPDN), besides alleviating routing congestion on the FS, considerably less dynamic and static IR drop values are predicted from on-chip power heat maps generated for a low power 64-bit CPU at 2nm design rules: 82% and 96% less (worst-case values) vs. a reference configuration, respectively. P/NMOS show similar or even superior I ON -I OFF after BS processing and extra anneal(s) added for V T recovery, mobility and BTI improvement - up to 8/15% higher I ON linked to anneal selection.