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Scaled FinFETs Connected by Using Both Wafer Sides for Routing Via Buried Power Rails

A. Veloso,A. Jourdain,D. Radisic,R. Chen,G. Arutchelvan,B. O'Sullivan,H. Arimura,M. Stucchi,A. De Keersgieter,M. Hosseini,T. Hopf,K. D'have,S. Wang,E. Dupuy,G. Mannaert,K. Vandersmissen,S. Iacovo,P. Marien,S. Choudhury,F. Schleicher,F. Sebaai,Y. Oniki, X. Zhou,A. Gupta,T. Schram,B. Briggs,C. Lorant,E. Rosseel,A. Hikavyy,R. Loo,J. Geypen,D. Batuk,G. T. Martinez,J. P. Soulie,K. Devriendt,B. T. Chan,S. Demuynck,G. Hiblot,G. Van der Plas,J. Ryckaert,G. Beyer,E. Dentoni Litta,E. Beyne,N. Horiguchi

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

Cited 12|Views74
Key words
Backside (BS) connectivity,buried power rails (BPRs),finFET,frontside (FS) and BS routing,transistor
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