Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
arxiv(2022)
摘要
We propose Sectored DRAM, a new, low-overhead DRAM substrate that reduces
wasted energy by enabling fine-grained DRAM data transfers and DRAM row
activation. Sectored DRAM leverages two key ideas to enable fine-grained data
transfers and row activation at low chip area cost. First, a cache block
transfer between main memory and the memory controller happens in a fixed
number of clock cycles where only a small portion of the cache block (a word)
is transferred in each cycle. Sectored DRAM augments the memory controller and
the DRAM chip to execute cache block transfers in a variable number of clock
cycles based on the workload access pattern with minor modifications to the
memory controller's and the DRAM chip's circuitry. Second, a large DRAM row, by
design, is already partitioned into smaller independent physically isolated
regions. Sectored DRAM provides the memory controller with the ability to
activate each such region based on the workload access pattern via small
modifications to the DRAM chip's array access circuitry. Activating smaller
regions of a large row relaxes DRAM power delivery constraints and allows the
memory controller to schedule DRAM accesses faster.
Compared to a system with coarse-grained DRAM, Sectored DRAM reduces the DRAM
energy consumption of highly-memory-intensive workloads by up to (on average)
33
Sectored DRAM's DRAM energy savings, combined with its system performance
improvement, allows system-wide energy savings of up to 23
DRAM chip area overhead is 1.7
believe that Sectored DRAM's ideas and results will help to enable more
efficient and high-performance memory systems. To this end, we open source
Sectored DRAM at https://github.com/CMU-SAFARI/Sectored-DRAM.
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