Low contact resistance side-interconnects strategy for epi-graphene based electronic integration

One of the reasons why graphene attracts so much attention is its large ballistic transport mean free path, which could lead to novel electronic devices with very low power dissipation, breaking one of the key barriers that currently limit further electronics miniaturization. In particular, epi-graphene with scalable growth and high compatibility with modern semiconductor fabrication procedures, make it the most promising candidate for graphene based integrated circuits. However, in order to preserve that power advantage, it is essential to create interconnections with low contact resistance. This has been a long-standing challenge as metal contacts directly deposited on graphene tend to form weak interfaces, and any impurities and processing residues on graphene can deteriorate its electrical properties. In this work, side contacts with low resistance are fabricated to connect to the edge of epitaxial graphene grown on the non-polar face of silicon carbide. The procedure starts by depositing aluminum oxide on graphene, which serves both as protective coating and dielectric layer, before device fabrication. To assure obtaining a high quality Al 2 O 3 layer using Atomic Layer Deposition (ALD), graphene is treated by hydrogen through plasma enhanced chemical vapor deposition forming reversible hydrogen functionalization. This is followed by ALD to grow a 15 nm-thick oxide, which covers the epitaxially grown graphene on SiC. Finally, the edge contact is built to connect to the single layer graphene, reaching remarkably low contact resistance width of about 340 Ω µm.