Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2022)

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摘要
This article proposes an unsupervised online spike sorter, dedicated to brain-implantable neural recording microsystems. The main (online) spike sorting phase in the proposed approach is based on the wave shape resemblance between spike classes, realized by template matching. This phase follows an offline training phase, implemented off the implant. In the training phase, the number and centroids of the clusters are automatically determined and subsequently sent to the implant to configure the on-implant online spike sorter. Comprehensively verified using two separate datasets with a wide spectrum of spike wave shapes, the proposed approach presents average classification accuracies of $\sim 85$ % (unsupervised) and $\sim 92$ % (supervised). A 64-channel spike sorter was designed using a computational core with folded architecture. To make the very large-scale integration (VLSI) implementation of this spike sorter appropriate for brain implants in terms of both power and area consumption, the computations realizing the proposed approach were significantly reduced. Designed in a standard 180-nm CMOS technology, the circuit consumes $1.74~\mu \text{W}$ /channel and per-channel area of 0.047 mm 2 . The circuit is capable of clustering neural spikes in real-time with a latency of as short as 1.36 ms. A prototype of the circuit was implemented and successfully tested.
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关键词
Brain implants,correlation coefficient,implantable neural signal processor,template matching,unsupervised online spike sorting
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