Pseudo-Static 1T Capacitorless DRAM using 22nm FDSOI for Cryogenic Cache Memory

Cryogenic CMOS processors need low latency, high bandwidth access to high-density on-die cache memory to maximize performance. In this work, we experimentally demonstrate, for the first time, pseudo-static random access memory operation of a 1T Capacitorless Floating Body DRAM using 22nm FDSOI transistor, down to 4.8K, suitable for cryogenic cache memory. We demonstrate a 1T Cryo-DRAM $(\mathrm{W}/\mathrm{L}_{\mathrm{G}}=120\text{nm}/20\text{nm})$ that exhibit: (a) record high sensing current and sense margin $(\Delta \mathrm{I}_{\text{Read}}=\mathrm{I}_{\text{Read}, 1}-\mathrm{I}_{\text{Read}, 0})$ , (b) pseudo-static retention characteristics (>10 ⁵ sec); (c) high write endurance > 10 ¹⁰ cycles, and (d) non-destructive read cycles > 10 ¹⁶ , suitable for cache application. Benchmarking reveals that 1T Cryo-DRAM outperforms Cryo-SRAM and Cryo-STT-MRAM in memory density by 10x and 50x; in read/write energy by 2.7x/2.4x and 1.3x/1.5x and in read latency by 1.46x and 1.80x respectively for a cache size of 2MB. Hence, 1T Cryo-DRAM is a viable option for L2/L3 cache in high-performance cryogenic computing.