A high-range reference voltage low-dropout regulation design for voltage-controlled oscillator circuit

Abstract The stability of VCO as a clock recovery module in high-speed transmission circuits cannot be ignored. The LDO circuit as its power module not only needs to ensure the stability of the VCO under high-speed working conditions, but also needs to satisfy the demand for changes in its supply voltage swing. To meet the above requirements, a high-range reference voltage LDO (Low-dropout Regulator) was designed under the 28nm process. The input of the error amplifier of the LDO adopts a rail-to-rail structure, the reference voltage can be changed in a larger range, and the output voltage can also fluctuate in the range of 0.3V-0.9V. After simulation, the power supply rejection ratio (PSRR) of this LDO is 1.53MHz, the line regulation at full load is 8.29mV/V, the internal noise of the circuit is low, the transient response time from on load to full load is 42ns, and the phase margin is close to 80deg.