Extended Carrier Lifetime in Epitaxial Ge-on-Nothing Virtual Substrates

Owing to its compatibility with mainstream Si technologies and remarkable physical properties, Ge has become a key enabler of modern semiconductor devices. In the past decades, the element has been introduced in various application areas such as high-performance and high-speed electronics, integrated photonics, photovoltaics, sensors and spintronics [1-2]. Its alloying with Si has for instance benefited the performance and power consumption of bipolar and CMOS transistors thanks to an increase in source/drain active doping concentration and channel carrier mobility. In its pure form, Ge has drawn a lot of attention for the integration of Ge nMOS devices [3-4], near-to-mid-infrared photodetectors and modulators [5-6] and as a substrate for multijunction solar cells [7], for which carrier mobility and lifetime are critical parameters. The fabrication of high-quality, scalable, relatively thin although fully relaxed Ge/Si virtual substrates (VS) is of utmost importance to enable and integrate these technologies at reduced costs. The monolithic epitaxial growth of Ge on Si however suffers from intrinsic limitations, due to the large lattice mismatch between the two materials inevitably causing the formation of a high-density network of misfit dislocations at the Ge/Si heterointerface. The inherent presence of large quantities of non-radiative recombination centers in this region has so far restricted the industrial use of Ge VS. Keeping the charge carriers away from the interface could nevertheless be in most cases an appropriate solution to contain their detrimental impact [8]. Growing thick Ge layers is a way to achieve this goal and reduce the material defectivity [9]. Unfortunately, quality improvements are limited and thicknesses exceeding 5 µm required to enter the sub 1E6 cm-2 threading dislocation density (TDD) range. This makes the process very time-consuming, expensive and induces a severe wafer bow. Another possibility consists in suppressing the defective part of the material. This can be done by splitting the Ge VS to isolate the top part of the layer from the Ge/Si interface. This method allows for performance improvements in case the replacement interface does not incur a greater penalty. In this contribution, we therefore evaluate the properties of Ge-on-nothing (GeON) suspended foils and benchmark extracted carrier lifetimes against those measured in blanket Ge/Si with different thicknesses. The concept, initially introduced by Sato et al. [10] and developed by imec to form silicon-on-nothing [11], is here applied to Ge VS, as presented in [12]. The process results in a ~ 1.2-1.4 µm thick Ge foil separated from the substrate (Figure 1) and is compared with blanket Ge VS with thicknesses ranging from 0.2 to 4.9 µm. Electron channeling contrast imaging (ECCI) and time-resolved photoluminescence (TR-PL) spectroscopy at the Ge direct bandgap are used to estimate the threading dislocation density and the free-carrier lifetime in the samples, respectively. Figure 2 and Table 1 summarize the results of this study. As expected, the estimated TDD decreases with increasing the Ge layer thickness. A minimum TDD value of ~ 4E6 cm-2 is obtained with the thicker Ge film (~ 4.9 µm thick, sample F). The GeON sample (sample D), does not stand out of the trend. On the other hand, the carrier lifetime obtained in sample D (> 30 ns) clearly outperforms those obtained for the different Ge VS (< 15 ns). This indicates that the recombination velocity at the newly formed Ge bottom surface is much lower than the one initially introduced by the defective Ge/Si interfacial region. Containing the carriers closer to this area by decreasing the thickness of the Ge VS strongly degrades their lifetime and compromises the material optical properties. We infer that GeON foils have an interesting potential for applications necessitating maximal lifetimes. References: [1] M. Bosi and G. Attolini, Progress in Crystal Growth and Characterization of Materials, 56(3-4), 146 (2010); [2] D. Paul, Semiconductor Science and Technology, 19 R75 (2004); [3] M. J. H. van Dal et al., IEEE International Electron Devices Meeting, 492 (2018); [4] H. Arimura et al., IEEE Transactions on Electron Devices, 66(12), 5387 (2019); [5] D. Marris-Morini et al., Nanophotonics, 7(11), 1781 (2018); [6] H. Chen et al., Journal of Lightwave Technology, 35(4), 722 (2017); [7] H. Cotal et al., Energy Environ. Sci., 2, 174 (2009); [8] R. Geiger et al., Applied Physics Letters, 104, 062106 (2014); [9] G. Wang et al., Applied Physics Letters, 94(10), 102115 (2009); [10] T. Sato et al., Symposium on VLSI Technology Digest Technical Papers, 206 (1998); [11] V. Depauw et al., Thin Solid Films, 516(20), 6934 (2008); [12] R. Loo et al., ECS Transactions, 98(5), 195 (2020). Figure 1