Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.