Relatively Low-k Ferroelectric Nonvolatile Memory Using Fast Ramping Fast Cooling Annealing Process

Hafnia-based ferroelectric field-effect transistors (FeFETs) with low power, scalability, and nonvolatile switching can overcome the performance limitations of conventional von Neumann computing technology. However, achieving a large memory window and excellent endurance in FeFET devices composed of two capacitors, such as ferroelectric and interfacial insulator capacitors, remains a challenge due to the strong electric field applied to the insulator, which accounts for the low permittivity (k) of interfacial insulator. In addition, write disturb (WD) is considered to be a hurdle in the practical array operation of 1T-type FeFET devices. In this study, we propose a core process in which the dielectric constant and grain size of hafnia ferroelectric are adjusted by the ramping/cooling process, achieving high speed (20 ns), high reliability (10(1)SUPERSCRIPT ZERO), and negligible disturb (0 V in 1/3 $V_{dd}$ operation) FeFET. This results from effective voltage drop and switching across a relatively low-k ferroelectric capacitor that is connected with an interfacial insulator. Intriguingly, using low-k HfZrO as a gate, the proposed 3-D structure FeFET exhibits an improved memory window and robustness in WD in the array operation. These results suggest an informative way to design a high memory performance of FeFETs for future applications.